• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.
    公开号:SU1076001A3
    申请号:SU782630256
    申请日:1978-06-29
    公开日:1984-02-23
    发明作者:Лахман Джоши Мадхукар；Дэвид Прайсер Вильбар
    申请人:Интернэшнл Бизнес Машинз Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

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    The invention relates to computing and can be used to organize semiconductor memory devices.
    Cells of memory for an integral matrix accumulator are known which require the use of two active elements and two address lines l | ,
    Closest to the proposed is a memory cell containing dictionary and bit buses, a reference potential bus and a serially connected key and a charge accumulator, with one pin of the key and a resistor connected to the discharge bus and the reference potential bus 2).
    Famous memory cell occupies a large area.
    The aim of the invention is to increase the degree of cell integration.
    This goal is achieved by the fact that the memory cell for an integral matrix storage device contains vocabulary and bit buses, a reference potential bus and a serially connected key and a charge accumulator on a capacitor and a resistor, with one pin of the key and a resistor connected to the bit bus and a reference potential bus, an amplifier is inserted, the control input of which is connected to a different output of the resistor, the bias input is connected to the reference potential bus, and the output is connected to another output of a switch, the control electrode Oogo is connected to the word line.
    The drawing shows the proposed device.
    The proposed device includes a vocabulary bus 1, a discharge bus 2, a key 3, a charge accumulator of a capacitor 4 and a resistor 5, an amplifier 6 and a bus 7 that support potential.
    The device works in the same way.
    The information is recorded on the capacitor 4 due to the fact that the discharge of the bus 2 has a preliminary charge, while the key 3, which is rectified at the field-effect transistor, is opened. To record zero information, the discharge bus is charged to a lower potential, for example, the ground potential, and since the discharge of the bus is at a zero potential, the capacitor is not charged.
    To read information, a potential is applied to the parallel bus and a pulse from the word bus closes the key. If 1 was recorded in the capacitor, the potential at the bit bus remains at the main level, and the amplifier b does not work. If O was recorded on the capacitor, i.e. Since capacitor 4 is not charged, the potential from the discharge bus charges the capacitor 4-, and a voltage appears on the resistor 5 that is applied to the input of amplifier 6 and opens it. In this case, the tire discharge through the key 3 and the amplifier b is discharged to the ground.
    权利要求:
    Claims (1)
    [1]
    MEMORY CELL FOR AN INTEGRAL MATRIX DRIVE, containing a dictionary and a discharge bus, a reference potential bus and series connected key and a charge storage device on a capacitor and a resistor, wherein one terminal of a key and a resistor are connected respectively to a discharge bus and a reference potential bus, characterized in that that, in order to increase the degree of integration of the cell, an amplifier is introduced into it, the control input of which is connected to the other terminal of the resistor, the bias input is connected to the reference potential bus, and the output is connected to the other terminal and whose control electrode soedinen.so word line.
    1076 001 A
    类似技术:
    公开号 | 公开日 | 专利标题
    US4247791A|1981-01-27|CMOS Memory sense amplifier
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    SU654197A3|1979-03-25|Semiconductor memory
    US4144590A|1979-03-13|Intermediate output buffer circuit for semiconductor memory device
    US4099265A|1978-07-04|Sense line balance circuit for static random access memory
    US3699544A|1972-10-17|Three transistor memory cell
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    US4360896A|1982-11-23|Write mode circuitry for photovoltaic ferroelectric memory cell
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    KR870002585A|1987-03-31|Semiconductor memory device
    US3629612A|1971-12-21|Operation of field-effect transistor circuit having substantial distributed capacitance
    US4255679A|1981-03-10|Depletion load dynamic sense amplifier for MOS random access memory
    US4418401A|1983-11-29|Latent image ram cell
    GB1243588A|1971-08-18|Capacitor memory circuit
    US3936810A|1976-02-03|Sense line balancing circuit
    EP0189908B1|1992-10-28|Dynamic memory with improved arrangement for precharging bit lines
    US4926379A|1990-05-15|Data read circuit for use in semiconductor memory device
    US4023147A|1977-05-10|Associative capacitive storage circuits
    同族专利:
    公开号 | 公开日
    JPS5813997B2|1983-03-16|
    IT1112637B|1986-01-20|
    AU514832B2|1981-02-26|
    ATA322178A|1983-05-15|
    IT7824494D0|1978-06-13|
    FR2396386A1|1979-01-26|
    DE2818783B2|1980-03-20|
    CH636469A5|1983-05-31|
    SE7806951L|1978-12-31|
    US4168536A|1979-09-18|
    GB1563479A|1980-03-26|
    DD141082A5|1980-04-09|
    AU3488378A|1979-10-11|
    AT373432B|1984-01-25|
    BE868453A|1978-10-16|
    BR7803995A|1979-04-03|
    ES470267A1|1979-09-16|
    DE2818783A1|1979-01-04|
    NL7807049A|1979-01-03|
    DE2818783C3|1980-11-27|
    FR2396386B1|1982-11-26|
    CA1114504A|1981-12-15|
    JPS5413234A|1979-01-31|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US3618053A|1969-12-31|1971-11-02|Westinghouse Electric Corp|Trapped charge memory cell|
    US3652914A|1970-11-09|1972-03-28|Emerson Electric Co|Variable direct voltage memory circuit|
    US3827034A|1972-09-14|1974-07-30|Ferranti Ltd|Semiconductor information storage devices|
    DE2456893B2|1974-12-02|1980-03-06|Siemens Ag, 1000 Berlin Und 8000 Muenchen|JPS5619585A|1979-07-26|1981-02-24|Toshiba Corp|Semiconductor memory unit|
    GB2070329B|1980-01-25|1983-10-26|Tokyo Shibaura Electric Co|Semiconductor memory device|
    JPS5948477B2|1980-03-31|1984-11-27|Fujitsu Ltd|
    DE3689004T2|1985-02-13|1994-01-20|Toshiba Kawasaki Kk|Semiconductor memory cell.|
    US4677589A|1985-07-26|1987-06-30|Advanced Micro Devices, Inc.|Dynamic random access memory cell having a charge amplifier|
    US5003361A|1987-08-31|1991-03-26|At&T Bell Laboratories|Active dynamic memory cell|
    CA1322250C|1987-08-31|1993-09-14|Loren Thomas Lancaster|Active dynamic memory cell|
    JP2575152B2|1987-10-22|1997-01-22|日宝化学株式会社|Iodine recovery equipment|
    US4999811A|1987-11-30|1991-03-12|Texas Instruments Incorporated|Trench DRAM cell with dynamic gain|
    US4914740A|1988-03-07|1990-04-03|International Business Corporation|Charge amplifying trench memory cell|
    US4970689A|1988-03-07|1990-11-13|International Business Machines Corporation|Charge amplifying trench memory cell|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US05/811,812|US4168536A|1977-06-30|1977-06-30|Capacitor memory with an amplified cell signal|
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